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Method of fabricating and integrating high quality decoupling capacitors

Patent image
NSA

Method of making an integrated passive, such as a high quality decoupling capacitor, includes providing a first temporary support, a silicon capacitor wafer, and providing an oxide layer and a conductive layer on it. Then, a second temporary support, such as a handle wafer, may be attached to the capacitor wafer (i.e., to the oxide layer on it) by an adhesive bond. The capacitor wafer may then be destructively removed. A second conductive layer is then provided on an exposed backside of the oxide layer. The addition of a second electrode on the second conductive layer yields the desired high quality capacitor. Further processing steps, such as solder bumping, may be carried out while the capacitor wafer is still attached to the handle wafer. When the desired processing steps are complete, the handle wafer is removed, and the relatively thin high quality integrated capacitor wafer results.

Inventors: 
Mountain, David Jerome
Patent Number: 
Technical domain: 
Electronics and Energy
FIle Date: 
2005-06-09
Grant Date: 
2007-11-20
Grant time: 
894 days
Grant time percentile rank: 
16
Claim count percentile rank: 
7
Citations percentile rank: 
1
'Cited by' percentile rank: 
1
Assignee: 
NATIONAL SECURITY AGENCY